Meaning
Measurement of the uncertainty in the sample-and-hold latching time of an analog-to-digital converter defines the variation in the actual sampling instant. The aperture jitter occurs when the clock signal has small timing variations that cause the converter to digitize the analog input at slightly irregular intervals. In high-frequency signal acquisition, this timing error translates directly into voltage noise, which degrades the signal-to-noise ratio.
The phenomenon is separate from aperture delay, which is the fixed propagation delay between the clock edge and the actual sampling switch closure.
Temporal Variation
Factors affecting this parameter include internal thermal noise within the sample-and-hold circuit and the transition slope of the sampling clock. A slower clock rise time makes the decision threshold more vulnerable to noise, increasing the effective uncertainty. Circuit designers minimize these effects by using high slew rate clock signals and ultra-low-noise buffer amplifiers.
Sampling Distortion
Calculating the effect of sampling uncertainty shows a clear relationship between input frequency and voltage error. The maximum voltage error is proportional to the product of the input signal slew rate and the timing uncertainty. For a high-frequency sinusoidal input, the voltage noise increases linearly with both the input frequency and the magnitude of the timing variation.
System Impact
In high-speed data acquisition systems, such as direct RF sampling receivers, timing uncertainty determines the achievable effective number of bits. A system designed for high bandwidth requires a clock with timing uncertainty in the femtosecond range to maintain signal fidelity. When the sampling frequency is high, this timing uncertainty becomes the dominant source of noise, limiting the performance of the system.
